Program methods for split-gate memory
US7495960B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2006 |
| Grant date | Feb 24, 2009 |
| Priority date | — |
| Expiry date | Oct 27, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array of flash memory cells includes a first sector comprising a plurality of rows wherein each row is connected to a control-gate line, a first row comprising a first flash memory cell in the first sector, a first control-gate line connecting control-gates of flash memory cells in the first row, a second row in the first sector and comprising a second flash memory cell sharing a common source-line and a same bit-line with the first flash memory cell, a second control-gate line connecting control-gates of memory cells in the second row wherein the first and the second control-gate lines are disconnected from each other, a second sector comprising a plurality of rows wherein each row is connected to a control-gate line, and a positive high-voltage (HV) driver connected to the first control-gate line in the first sector and a control-gate line in the second sector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.