Stacked integrated circuit package-in-package system
US7498667B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2006 |
| Grant date | Mar 3, 2009 |
| Priority date | — |
| Expiry date | Jan 3, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked integrated circuit package-in-package system is provided forming a first integrated circuit package having a first peripheral contact, forming a second integrated circuit package having a second peripheral contact, stacking the second integrated circuit package on the first integrated circuit package in a multidirectional offset stack configuration with the first peripheral contact exposed, the multidirectional offset stack configuration provides a second package overhang with the second integrated circuit package above the first integrated circuit package, electrically connecting the first peripheral contact and a package substrate contact along a package first edge, and electrically connecting the second peripheral contact and the package substrate contact along a package second edge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.