Implementation of low power standby modes for integrated circuits
US7498835B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2005 |
| Grant date | Mar 3, 2009 |
| Priority date | — |
| Expiry date | Jan 26, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A PLD (200) includes a power management unit (PMU 210) that selectively implements one or more different power-reduction techniques in response to power configuration signals (PC). By manipulating the PC signals, the PMU can independently enable/disable various supply voltage circuits (110, 120, 130) that power CLBs (101), IOBs (102), and configuration memory cells (106), can generate a capture signal that causes data stored in storage elements of the CLBs to be captured in configuration memory cells, and/or can switch power terminals of configuration memory cells between voltage supply circuits. Also, the PMU can sequentially apply and remove power from a number of configurable PLD portions in response to the PC signals, wherein each configurable portion may include any number of the PLD's resources.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.