Flash memory device with improved erase operation
US7499325B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2006 |
| Grant date | Mar 3, 2009 |
| Priority date | — |
| Expiry date | Jan 31, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments include a device having memory cells coupled to a well of a semiconductor substrate, and a select transistor coupled between the memory cells and a bit line of the device. The device may have a first circuit to raise a well voltage of the well from a first well voltage level to a second well voltage level during an erase operation. The first circuit may hold the well at the second well voltage level for a time interval during the erase operation. The device may have a second circuit to raise a voltage of the gate of the select transistor from a first gate voltage level to a second gate voltage level, which may be lower than the second well voltage level. The second circuit may hold the gate at the second gate voltage level for a time interval during the erase operation. Other embodiments including additional apparatus, systems, and methods are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.