Memory with resistance memory cell and evaluation circuit
US7499349B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 7, 2007 |
| Grant date | Mar 3, 2009 |
| Priority date | — |
| Expiry date | Feb 15, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit comprising a memory cell which has a resistance memory element and is connected between a ground terminal and a capacitor has a reference memory cell with a reference resistor which is connected between the ground terminal and a reference capacitor, in which case, during the reading operation of the memory cell, the memory cell and the reference memory cell are switched on in order to charge or discharge the capacitor and the reference capacitor, and an evaluation device evaluates the difference between the electrical potentials of the capacitor and the reference capacitor at a predetermined instant after the switching-on of the memory cell and the reference memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.