Semiconductor memory device
US7499356B2 · kind B2 · utility
5Cited by
13References
39Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 28, 2006 |
| Grant date | Mar 3, 2009 |
| Priority date | — |
| Expiry date | Apr 9, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a plurality of first pads; a plurality of ports for performing a serial data communication with external devices through the first pads; a plurality of banks for performing a parallel data communication with the plurality of ports; a plurality of global data buses for supporting the parallel data communication between the plurality of ports and the plurality of banks; and a test mode controller for performing a core test with various data transfer modes by converting the serial data communication into the parallel data communication during a core test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.