Method and apparatus for selectively compacting test responses
US7500163B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Oct 25, 2004 |
| Grant date | Mar 3, 2009 |
| Priority date | — |
| Expiry date | Oct 25, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318547
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.