Multilayer OPC for design aware manufacturing
US7503028B2 · kind B2 · utility
4Cited by
6References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2006 |
| Grant date | Mar 10, 2009 |
| Priority date | — |
| Expiry date | Apr 19, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/36
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper functional interaction, while relaxing or eliminating the EPE constraints on the location of the wafer images.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.