Level shifter translator
US7504862B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2005 |
| Grant date | Mar 17, 2009 |
| Priority date | — |
| Expiry date | Dec 28, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01721
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Level shifter translator of the type comprising at least one first transistor and one second MOS transistor belonging to respective circuit branches connected with a first common conduction terminal and connected towards a first potential reference and receiving, on the respective conduction terminals, input differential voltages, the first and the second transistor have respective circuit branches referring to a biasing circuit with current mirror, a third transistor allows to couple the second transistor to said biasing circuit, an inverter connected to an output of said the circuit with the output driving the third transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.