Decompressor/PRPG for applying pseudo-random and deterministic test patterns
US7506232B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Aug 11, 2006 |
| Grant date | Mar 17, 2009 |
| Priority date | — |
| Expiry date | Aug 11, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318547
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.