IGBT with amorphous silicon transparent collector
US7507608B2 · kind B2 · utility
0Cited by
6References
9Claims
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Key dates
| Filing date | Dec 8, 2005 |
| Grant date | Mar 24, 2009 |
| Priority date | — |
| Expiry date | Mar 10, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/142
Abstract
The collector or anode of a non-punch through IGBT formed in a float zone silicon wafer is formed by a P doped amorphous silicon layer deposited on the back surface of an ultra thin wafer. A DMOS structure is formed on the top surface of the wafer before the bottom structure is formed. A back contact is formed over the amorphous silicon layer. No alloy step is needed to activate the anode defined by the P type amorphous silicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.