Extending incremental verification of circuit design to encompass verification restraints
US7509605B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2005 |
| Grant date | Mar 24, 2009 |
| Priority date | — |
| Expiry date | Feb 18, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An incremental verification method includes eliminating verification constraints from a first netlist and using the resulting netlist to create a constraint-free composite netlist suitable for determining equivalence between the first netlist and a second netlist of a design. Eliminating a constraint from a netlist may include adding a modified constraint net where the modified constraint net is FALSE for all cycles after any cycle in which the original constraint is FALSE. The method may include, instead of eliminating constraints, determining that the verification result is a target-not-asserted result and that the second netlist constraints are a superset of the first netlist constraints or that the verification result is a target-asserted result and that the first netlist constraints are a superset of the second netlist constraints. In either case, the method may include creating the composite netlist by importing all of the original constraints into the composite netlist.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.