Nonvolatile memory cell with multiple floating gates and a connection region in the channel
US7511333B2 · kind B2 · utility
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11References
17Claims
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Key dates
| Filing date | Oct 6, 2005 |
| Grant date | Mar 31, 2009 |
| Priority date | — |
| Expiry date | Mar 31, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0491
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell (110) has a plurality of floating gates (120L, 120R). The channel region (170) comprises a plurality of sub-regions (220L, 220R) adjacent to the respective floating gates, and a connection region (210) between the floating gates. The connection region has the same conductivity type as the source/drain regions (160) to increase the channel conductivity. Therefore, the floating gates can be brought closer together even though the inter-gate dielectric (144) becomes thick between the floating gates, weakening the control gate's (104) electrical field in the channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.