DFN semiconductor package having reduced electrical resistance
US7511361B2 · kind B2 · utility
7Cited by
0References
8Claims
0Family size
Inventors
Key dates
| Filing date | Jun 10, 2005 |
| Grant date | Mar 31, 2009 |
| Priority date | — |
| Expiry date | Jun 10, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A DFN semiconductor package is disclosed. The package includes a leadframe having a die bonding pad formed integrally with a drain lead, a source lead bonding area and a gate lead bonding area, the source lead bonding area and the gate lead bonding area being of increased area, a die coupled to the die bonding pad, a die source bonding area coupled to the source lead bonding area and a die gate bonding area coupled to the gate lead bonding area, and an encapsulant at least partially covering the die, drain lead, gate lead bonding area and source lead bonding area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.