Semiconductor chip arrangement and method

US7511382B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Edmund Riedl · Bergneustadt, DE
• Ralf Otremba · Kaufbeuren, DE
• Ivan Galesic · Regensburg, DE

Key dates

• Filing date: May 3, 2005
• Grant date: Mar 31, 2009
• Expiry date: May 24, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3511
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor chip arrangement and method is disclosed. In one embodiment, the invention provides a method for providing a semiconductor chip arrangement including providing a semiconductor chip having a first connecting area, and providing a chip carrier having a concave shaped section formed in a second connecting area. A connecting mechanism is provided between the first connecting area and the second connecting area and pressing the semiconductor chip onto the chip carrier such that the connecting mechanism positively locks the first connecting area to the concave shaped section of the second connecting area.