Protecting an integrated circuit test mode
US7512852B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2005 |
| Grant date | Mar 31, 2009 |
| Priority date | — |
| Expiry date | Nov 14, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318536
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An electronic circuit, including; a logic circuit having a plurality of logic cells; storage cells able to form a shift register, able to be connected to the logic cells; a connecting control module having an input for the reception of an identification key, the module connecting the storage cells so as to form a test shift register when the receive input receives a valid identification key, and the module connecting the storage cells so as to form randomly a diversion circuit when the input does not receive a valid identification key. The invention allows the electronic circuit to be protected against fraudulent access in read or write mode. The invention also relates to a smart card including this electronic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.