Techniques for mitigating, detecting, and correcting single event upset effects in systems using SRAM-based field programmable gate arrays
US7512871B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2006 |
| Grant date | Mar 31, 2009 |
| Priority date | — |
| Expiry date | Sep 4, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic outputs and voter circuits in feedback loops; enhanced triple device redundancy using three FPGAs is introduced to provide nine instances of the user's logic; critical redundant outputs are wire-ANDed together; redundant dual port RAMs, with one port dedicated to refreshing data; and redundant clock delay locked loops (DLL) are monitored and reset if each DLL does not remain in phase with the majority of the DLLs. Detection techniques include: configuration memory readback wherein a checksum is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array. Correction techniques include reconfiguration of partial configuration data and “scrubbing” based on anticipated SEUs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.