Aligning stacked chips using resistance assistance
US7514276B1 · kind B1 · utility
6Cited by
9References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2008 |
| Grant date | Apr 7, 2009 |
| Priority date | — |
| Expiry date | Aug 12, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a method of aligning stacked chips wherein the apparatus and method utilize bumps in the form of exposed metal lines on a first chip. The present invention further relates to taking a resistance measurement to determine a quality of alignment wherein the resistance measurement indicates a direction in which the first chip and the second chip are misaligned.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.