Method of manufacturing a SONOS memory
US7514311B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2007 |
| Grant date | Apr 7, 2009 |
| Priority date | — |
| Expiry date | Mar 2, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
A method of manufacturing a silicon-oxide-nitride-oxide-silicon (SONOS) memory is provided herein. In the method, a bottom silicon oxide layer is formed over a substrate. A patterned mask layer having a trench therein is formed over the bottom silicon oxide layer. A charge-trapping layer is formed over the substrate covering the surface of the trench. The charge-trapping layer is etched back to form a pair of charge storage spacers on the sidewalls of the trench. After removing the mask layer, a top silicon oxide layer is formed over the substrate covering the charge storage spacers and the bottom silicon oxide layer. A gate corresponding to the pair of charge storage spacers is formed on the top silicon oxide layer. A source/drain region is formed in the substrate on each side of the gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.