Semiconductor device and a method of manufacturing the same
US7514749B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2008 |
| Grant date | Apr 7, 2009 |
| Priority date | — |
| Expiry date | May 18, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/68
Abstract
A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger than the sum of the thickness of a polycrystalline silicon film serving as a gate electrode of a low breakdown voltage, the thickness of a gate insulating film and an alignment allowance in processing of a gate electrode in a direction orthogonal to the extending direction of the gate electrode and is larger than the thickness of the polycrystalline silicon film in a planar region not overlapping the gate electrode. It is possible to decrease the number of manufacturing steps for the semiconductor integrated circuit device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.