Patent · US Active

High density memory array for low power application

US7515455B2 · kind B2 · utility

14Cited by

4References

25Claims

0Family size

Assignee

Qimonda North America Corp. · US

Inventors

Thomas Nirshl · South Burlington, US
Thomas Happ · Tarrytown, US

Key dates

Filing date	Jan 5, 2007
Grant date	Apr 7, 2009
Priority date	—
Expiry date	Jan 5, 2027

Classification

Technology area (CPC G)Physics
CPC primaryG11C7/04
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory device includes a first bit line in a first conducting layer and a second bit line parallel to the first bit line. The second bit line is in a second conducting layer. The memory device includes a MOS select transistor and a word line coupled to a gate of the MOS select transistor. The word line is at an angle with respect to the first bit line and the second bit line. The memory device includes a first resistive memory element coupled between a source of the MOS select transistor and the first bit line. The memory device includes a second resistive memory element coupled between a drain of the MOS select transistor and the second bit line.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.