P-channel MOS transistor and fabrication process thereof
US7518188B2 · kind B2 · utility
8Cited by
5References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 14, 2005 |
| Grant date | Apr 14, 2009 |
| Priority date | — |
| Expiry date | Jul 14, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
Abstract
A p-channel MOS transistor includes a gate electrode formed on a silicon substrate in correspondence to a channel region therein via a gate insulation film, the gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, and source and drain regions of p-type are formed in the substrate at respective outer sides of the sidewall insulation films, wherein each of the source and drain regions encloses a polycrystal region of p-type accumulating therein a compressive stress.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.