Reconfigurable SIMD vector processing system
US7519646B2 · kind B2 · utility
10Cited by
5References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2006 |
| Grant date | Apr 14, 2009 |
| Priority date | — |
| Expiry date | Aug 16, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system may include M N-bit×N-bit multipliers to output M 2N-bit products in a redundant format, a compressor to receive the M 2N-bit products and to generate an MN-bit product in a redundant format based on the M 2N-bit products, and an adder block to receive the M 2N-bit products and the MN-bit product, to select one from the M 2N-bit products or the MN-bit product, and to resolve the selected one of the M 2N-bit products or the MN-bit product to a non-redundant format.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.