Memory circuit, method for operating a memory circuit, memory device and method for producing a memory device
US7522444B2 · kind B2 · utility
0Cited by
6References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2006 |
| Grant date | Apr 21, 2009 |
| Priority date | — |
| Expiry date | May 24, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is related to a memory circuit comprising: a resistive memory element comprising a programmable metallization cell, a bit line, a selection transistor operable to address the resistive memory element for coupling the resistive memory element to the bit line, and a further transistor coupled with the resistive memory element for applying a predefined potential at a node between the selection transistor and the resistive memory element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.