Data input circuit of semiconductor memory device
US7522459B2 · kind B2 · utility
11Cited by
13References
69Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 30, 2006 |
| Grant date | Apr 21, 2009 |
| Priority date | — |
| Expiry date | May 26, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/107
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An input circuit can minimize a circuit area required for data prefetch operation for an increased bit number of prefetch data. A control signal generating unit generates a plurality of control signals in response to a clock signal and a data strobe signal, wherein external data are input in synchronism with the data strobe signal. A synchronizing unit for aligns the input data into N-bit data in parallel by performing a data alignment operation at least three times, N being a positive integer larger than one.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.