Fabrication method of wafer level chip scale packages
US7524763B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2005 |
| Grant date | Apr 28, 2009 |
| Priority date | — |
| Expiry date | Jun 7, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating wafer level chip scale packages may involve forming a hole to penetrate through a chip pad of an IC chip. A base metal layer may be formed on a first face of a wafer to cover inner surfaces of the hole. An electrode metal layer may fill the hole and rise over the chip pad. A second face of the wafer may be grinded such that the electrode metal layer in the hole may be exposed through the second face. By electroplating, a plated bump may be formed on the electrode metal layer exposed through the second face. The base metal layer may be selectively removed to isolate adjacent electrode metal layers. The wafer may be sawed along scribe lanes to separate individual packages from the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.