Stack package having guard ring which insulates through-via interconnection plug and method for manufacturing the same
US7525186B2 · kind B2 · utility
240Cited by
0References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2006 |
| Grant date | Apr 28, 2009 |
| Priority date | — |
| Expiry date | Feb 2, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stack package comprises a substrate having a circuit pattern; at least two semiconductor chips stacked on the substrate, having a plurality of through-via interconnection plugs and a plurality of guard rings which surround the respective through-via interconnection plugs, and connected with each other by the medium of the through-via interconnection plugs; a molding material for molding an upper surface of the substrate including the stacked semiconductor chips; and solder balls mounted to a lower surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.