Apparatus and method to manage external voltage for semiconductor memory testing with serial interface
US7525856B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2007 |
| Grant date | Apr 28, 2009 |
| Priority date | — |
| Expiry date | Oct 14, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/1201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A serial-interface flash memory device includes a data/address I/O pin and a clock input pin. A bidirectional buffer is coupled to the data/address I/O pin. A serial interface logic block including data direction control is coupled to the clock pin, the bidirectional buffer, to internal control logic, and to read-voltage and modify-voltage generators. A first switch is coupled to the read-voltage generator and the clock buffer and a second switch is coupled to the modify-voltage generator and the clock buffer, the first and second switches each having a control input. Memory drivers are coupled to the read-voltage generator and the modify-voltage generator through the first and second switches. First and second registers coupled between the serial interface logic and the first and second switches. A memory array is coupled to the memory drivers and read amplifiers and program buffers are coupled between the serial interface logic and the memory drivers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.