Stressor integration and method thereof

US7528029B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Paul A. Grudowski · Austin, US
• Darren V. Goedekc · Pflugerville, US
• John J. Hackenberg · West Melbourne, US

Key dates

• Filing date: Apr 21, 2006
• Grant date: May 5, 2009
• Expiry date: Apr 22, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0212

Abstract

A method is provided for making a semiconductor device. In accordance with the method, a substrate (203) is provided which has first (205) and second (207) gate structures thereon. A first stressor layer (215) is formed over the substrate, and a sacrificial layer (216) is formed over the first stressor layer. A second stressor layer (219) is formed over the sacrificial layer.