Three-dimensional package and method of making the same
US7528053B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2006 |
| Grant date | May 5, 2009 |
| Priority date | — |
| Expiry date | Aug 6, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01078
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional package and a method of making the same including providing a wafer; forming at least one blind hole in the wafer; forming an isolation layer on the side wall of the blind hole; forming a conductive layer on the isolation layer; forming a dry film on the conductive layer; filling the blind hole with metal; removing the dry film, and patterning the conductive layer; removing a part of the metal in the blind hole to form a space; removing a part of the second surface of the wafer and a part of the isolation layer, to expose a part of the conductive layer; forming a solder on the lower end of the conductive layer, the melting point of the solder is lower than the metal; stacking a plurality of the wafers, and performing a reflow process; and cutting the stacked wafers, to form three-dimensional packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.