Method for manufacturing gate oxide layer with different thicknesses
US7528076B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2007 |
| Grant date | May 5, 2009 |
| Priority date | — |
| Expiry date | Nov 28, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0144
Abstract
A method of manufacturing gate oxide layers with different thicknesses is disclosed. The method includes that a substrate is provided first. The substrate has a high voltage device region and a low voltage device region. Then, a high voltage gate oxide layer is formed on the substrate. Afterwards, a first wet etching process is performed to remove a portion of the high voltage gate oxide layer in the low voltage device region. Then, a second wet etching process is performed to remove the remaining high voltage gate oxide layer in the low voltage device region. The etching rate of the second wet etching process is smaller than that of the first wet etching process. Next, a low voltage gate oxide layer is formed on the substrate in the low voltage device region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.