Non-volatile semiconductor memory and method for controlling a non-volatile semiconductor memory
US7528447B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2006 |
| Grant date | May 5, 2009 |
| Priority date | — |
| Expiry date | Apr 5, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/681
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile semiconductor memory including a plurality of memory cell transistors, each of the plurality of memory cell transistors includes: a source region having a first conductivity type and in contact with a buried insulating layer on a supporting substrate; a drain region having the first conductivity type and in contact with the buried insulating layer; and a channel region having the first conductivity type and provided between the source region and the drain region so as to contact the buried insulating layer, wherein a thickness of the channel region is more than one nm and not more than a value obtained by adding seven nm to a half value of a gate length of the memory cell transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.