Chip structure
US7528495B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Oct 17, 2006 |
| Grant date | May 5, 2009 |
| Priority date | — |
| Expiry date | Oct 17, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip structure including a substrate, at least one chip bonding pad, a passivation layer, at least one compliant bump, and at least one redistribution conductive trace is provided. The substrate has an active surface whereon the chip bonding pad is disposed. The passivation layer is disposed on the active surface and exposes the chip bonding pad. The compliant bump has a top surface and a side surface. At least part of the compliant bump is disposed on the passivation layer. One end of the redistribution conductive trace is electrically connected to the chip bonding pad and the other end thereof covers part of the side surface and at least part of the top surface of the compliant bump. Therefore, the chip bonding pad of the chip structure can be electrically connected to the corresponding electrical contact of the carrier through the compliant bump and the redistribution conductive trace.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.