Testing of multiple asynchronous logic domains
US7529294B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2006 |
| Grant date | May 5, 2009 |
| Priority date | — |
| Expiry date | Mar 18, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31725
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A digital system and a method for operating the same. The digital system includes (a) a first and a second pins, (b) first and second logic domains, and (c) first and second test pulse generator circuits. The first test pulse generator circuit is electrically coupled to the first pin and the first logic domain. The second test pulse generator circuit is electrically coupled to the second pin and the second logic domain. When a first test signal and K (positive integer) common test enable signals being asserted, the first test pulse generator circuit generates two first test pulses resulting in the first logic domain being tested. When a second test signal and the K common test enable signals being asserted, the second test pulse generator circuit generates two second test pulses resulting in the second logic domain being tested. The first and second pins are connected to a tester.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.