Non-planar MOS structure with a strained channel region
US7531393B2 · kind B2 · utility
119Cited by
38References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2006 |
| Grant date | May 12, 2009 |
| Priority date | — |
| Expiry date | Mar 11, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6748
Abstract
An embodiment is a non-planar MOS transistor structure including a strained channel region. The combination of a non-planar MOS transistor structure, and in particular an NMOS tri-gate transistor, with the benefits of a strained channel yields improved transistor drive current, switching speed, and decreased leakage current for a given gate length width versus a non-planar MOS structure with an unstrained channel or planar MOS structure including a strained channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.