Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer

US7531404B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Sangwoo Pae · Beaverton, US
• Jose Maiz · Portland, US
• Justin K. Brask · Portland, US
• Gilbert Dewey · Beaverton, US
• Jack T. Kavalieros · Portland, US
• Robert S. Chau · Beaverton, US
• Suman Datta · Beaverton, US

Key dates

• Filing date: Aug 30, 2005
• Grant date: May 12, 2009
• Expiry date: Dec 7, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/018
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of forming a transistor gate stack having an annealed gate dielectric layer begins by providing a substrate that includes a first and second spacer separated by a trench. A conformal high-k gate dielectric layer is deposited on the substrate and within the trench with a thickness that ranges from 3 Å to 60 Å. Next, a capping layer is deposited on the high-k gate dielectric layer that substantially fills the trench and covers the high-k gate dielectric layer. The high-k gate dielectric layer is then annealed at a temperature that is greater than or equal to 600° C. The capping layer is removed to expose an annealed high-k gate dielectric layer. A metal layer is then deposited on the annealed high-k gate dielectric layer. A CMP process may be used to remove excess material and complete formation of the transistor gate stack.