Apparatus and method for a non-volatile memory structure comprising a multi-layer silicon-rich, silicon nitride trapping layer
US7531411B2 · kind B2 · utility
2Cited by
5References
18Claims
0Family size
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Key dates
| Filing date | Oct 12, 2005 |
| Grant date | May 12, 2009 |
| Priority date | — |
| Expiry date | Sep 2, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory structure comprises a trapping layer that includes a plurality of silicon-rich, silicon nitride layers. Each of the plurality of silicon-rich, silicon nitride layers can trap charge and thereby increase the density of memory structures formed using the methods described herein. In one aspect, the plurality of silicon-rich, silicon nitride layers are fabricated by converting an amorphous silicon layer by remote plasma nitrogen (RPN).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.