Method for forming an integrated semiconductor circuit arrangement

US7531439B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Johann Rieger · Monsheim, DE
• Stefan Lipp · Bad Liebenzell, DE
• Hans Zeindl · Altdorf, DE
• Thomas Detzel · Villach, AT
• Hubert Maier · Villach, AT

Key dates

• Filing date: May 26, 2005
• Grant date: May 12, 2009
• Expiry date: Feb 16, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/7684
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods for forming an integrated semiconductor circuit arrangement are disclosed. In one embodiment, a semiconductor circuit with a first semiconductor circuit region and with a second semiconductor circuit region is formed in each case in a semiconductor material region. A first metallization layer is applied to the structure thus obtained. A protective material region is then formed. A second metallization layer is subsequently applied, which is then also patterned. Afterward, the first metallization layer together with the protective material region is then patterned.