Method of fabricating semiconductor device having contact hole with high aspect-ratio
US7531450B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2007 |
| Grant date | May 12, 2009 |
| Priority date | — |
| Expiry date | Nov 13, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a method of fabricating a semiconductor device having a contact hole with a high aspect-ratio. The method includes: sequentially forming a lower pattern and an upper layer on a semiconductor substrate; sequentially forming a lower mask layer and an upper mask layer on the upper layer; sequentially patterning the lower and upper mask layers to form a hole exposing a top surface of the upper layer on the lower pattern; using the upper mask layer as an etching mask to anisotropically etch the exposed top surface to form an upper contact hole exposing a top surface of the lower pattern; and using the lower mask layer as an etching mask to anisotropically etch the exposed lower pattern to form a lower contact hole in the lower pattern, the lower contact hole extending from the upper contact hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.