Calibrated data communication system and method
US7535933B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2006 |
| Grant date | May 19, 2009 |
| Priority date | — |
| Expiry date | Jan 15, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.