BIST address generation architecture for multi-port memories
US7536613B2 · kind B2 · utility
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Key dates
| Filing date | May 11, 2004 |
| Grant date | May 19, 2009 |
| Priority date | — |
| Expiry date | Mar 24, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is testing multi-port array macros where latches and logic are used to control the relationship between the write and read port of the array. This makes allowance for many different configurations of reading and writing the array. This also allows for greater test coverage than the previous method, which simply inverted one of the write address bits to form the read address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.