Patent · US Active

Method for recognizing and verifying FIFO structures in integrated circuit designs

US7536662B2 · kind B2 · utility

6Cited by

4References

17Claims

0Family size

Assignee

Atrenta, Inc. · US

Inventors

Shaker Sarwary · San Diego, US
Jun Yuan · San Diego, US
Bernard Murphy · San Jose, US
Ashish Hari · Noida, IN
Paras Mal Jain · Cupertino, US

Key dates

Filing date	Jun 27, 2006
Grant date	May 19, 2009
Priority date	—
Expiry date	Apr 7, 2027

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/33
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

First-in-first-out (FIFO) structures are recognized and verified in integrated circuit (IC) designs. The FIFO recognition is based on structural analysis of the design. Specifically, the structural analysis includes performing seed based recognition by identifying logic elements that indicate the existence of candidate FIFO circuitry and then exploring the candidate circuitry to completely verify the presence of a FIFO structure. Recognized FIFOs may be verified to ensure the proper generation of the full and empty flags.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.