Determining networks of a tile module of a programmable logic device
US7536668B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2006 |
| Grant date | May 19, 2009 |
| Priority date | — |
| Expiry date | Apr 7, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor-implemented method is provided for determining networks of a tile module of a programmable logic device (PLD) design. A netlist describing the PLD design and a tile module identification are input. Characterization data is input for a sub-module of the tile module that specifies modeled pins of the sub-module, which is either a switchbox or a logic site. Connectivity pins of the tile module are determined. Each connectivity pin of one of the tile instances is connected in the netlist to a modeled pin of an instance of the sub-module within a tile instance. Networks of the tile module are determined that connect a first subset of the connectivity pins of the tile module and a second subset of the modeled pins of an instance of the sub-module within the tile module. A specification is output for each of the networks including the first subset and the second subset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.