Differential offset spacer
US7537988B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2007 |
| Grant date | May 26, 2009 |
| Priority date | — |
| Expiry date | Oct 20, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric and a plurality of gate electrodes thereon in both NMOS and PMOS regions using the surface. A multi-layer offset spacer stack including a top layer and a compositionally different bottom layer is formed and the multi-layer spacer stack is etched to form offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize a thinner offset spacer are covered with a first masking material, and transistors designed to utilize a thicker offset spacer are patterned and first implanted. At least a portion of the top layer is removed to leave the thinner offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize the thicker offset spacer are covered with a second masking material, and the transistors designed to utilize the thinner offset spacer are patterned and second implanted. The fabrication of the integrated circuit is then completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.