Resistive memory including refresh operation
US7539050B2 · kind B2 · utility
20Cited by
14References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2006 |
| Grant date | May 26, 2009 |
| Priority date | — |
| Expiry date | Nov 22, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes an array of resistive memory cells, a counter having an increment step based on temperature, and a circuit for refreshing the memory cells in response to the counter exceeding a preset value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.