Implementation of a fusing scheme to allow internal voltage trimming
US7539075B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2007 |
| Grant date | May 26, 2009 |
| Priority date | — |
| Expiry date | Oct 10, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for adjusting trim settings for internally generated voltages of an integrated circuit device are provided. In one embodiment the apparatus receives a target digital value for an internally generated voltage, and compares the target digital value to a current digital value for the internally generated voltage. If the comparison indicates that a difference between the target digital value and the current digital value is greater than an allowable threshold, a trim setting used to trim the internally generated voltage is adjusted based on the difference. The trim setting may be adjusted until the difference between the target digital value and the current digital value is less than or equal to the allowable threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.