Method for fabricating memory cell
US7541241B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2005 |
| Grant date | Jun 2, 2009 |
| Priority date | — |
| Expiry date | Jun 21, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/259
Abstract
A memory cell structure comprises a semiconductor substrate, two stack structures positioned on the semiconductor substrate, two conductive spacers positioned on sidewalls of the two stack structures, a gate oxide layer covering a portion of the semiconductor substrate between the two conductive spacers and a gate structure positioned at least on the gate oxide layer. Particularly, each of two stack structures includes a first oxide block, a conductive block and a second oxide block, and the two conductive spacers are positioned at on the sidewall of the two conductive blocks of the two stack structures. The two conductive spacers are preferably made of polysilicon, and have a top end lower than the bottom surface of the second oxide block. In addition, a dielectric spacer is positioned on each of the two conductive spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.