Apparatus for reading a multi-level passive element memory cell array
US7542337B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2006 |
| Grant date | Jun 2, 2009 |
| Priority date | — |
| Expiry date | Apr 19, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/77
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A four level passive element cell has memory states corresponding to decreasing resistance levels, which are preferably mapped respectively to data states 11, 01, 00, and 10. The LSB and MSB are preferably mapped as part of different pages. To discriminate between memory cell states, the selected bit line current is sensed for at least two different combinations of reference current level and read bias voltage. A mid-level reference is used to read the LSB. When reading the MSB, a first reference between the 10 and 00 data states, and a second reference between 01 and 11 data states may be used, and the mid-level reference need not be used. In certain embodiments, the bit line current may be simultaneously compared against the first and second references, without requiring a delay to stabilize the bit line current to a different value, and the MSB generated accordingly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.