Integrated circuit featuring a non-volatile memory with charge/discharge ramp rate control and method therefor
US7542351B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2007 |
| Grant date | Jun 2, 2009 |
| Priority date | — |
| Expiry date | Aug 3, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (10) comprises a plurality of non-volatile memory cells (14) and a charge distribution ramp rate control circuit (11). Each memory cell of the array (12) includes a charge storage region and a plurality of terminals. The charge distribution ramp rate control circuit includes a capacitor (62,116,144) having a first plate electrode coupled to at least one terminal of the plurality of terminals, and a second plate electrode. The charge distribution ramp rate control circuit further includes a bandgap generated current source (58,106,136) for providing a reference current to determine a ramp rate of a voltage at the at least one terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.