Programmable bias for a memory array
US7542360B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2007 |
| Grant date | Jun 2, 2009 |
| Priority date | — |
| Expiry date | Dec 9, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/12005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method determines a body bias for a memory cell. A supply voltage is applied to the memory cell and a bit line is precharged to a voltage lower than the supply voltage. A programmable bias voltage circuit provides a bias voltage to the memory cell in response to values on its input. Initial test values for the input are used. The memory cell is tested to determine a pass or a fail condition of the memory cell. The initial values are retained as the input values if the memory cell passes. If the memory cell fails, the memory cell is tested at changed values for the input. If the changed input values result in the memory cell being in a pass condition, the programmable bias voltage circuit is configured, in non-volatile fashion, to have the changed input values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.